The original QFN IC was designed by Amkor Technology, Inc. of Chandler, Ariz., but other companies also make and sell QFN IC packages, such as Texas Instruments Incorporated of Dallas, Tex. The typical QFN IC package comprises an IC die mounted on a paddle, which, in turn, is attached to a metal leadframe. The metal leadframe is wire bonded during a wire bonding process to connect the input/output (I/O) pads of the IC die to external lands of the package. The die attach and wire bonding processes are normally performed simultaneously on many like QFN IC packages while they are attached to the same leadframe. An over molding process is then performed during which the leadframe assembly having the QFN IC packages attached to it is over molded in plastic. After the over molding process has been performed, a singulation process is performed to separate the IC packages from the leadframe into individual IC packages. The resulting IC package is a square or rectangular package having external package lands for connecting the package to a PWB or PCB. These external package lands are exposed and flush around the bottom perimeter of the package. The paddle that the IC is mounted on is also flush and exposed on the bottom of the package.
The final QFN IC package is soldered onto a PWB or PCB by soldering the paddle located on the bottom of the package to the PWB or PCB. The PWB or PCB designer then routes traces on the PWB or PCB to the individual lands of the IC package, which are then electrically connected by soldering to make the electrical connections between the IC lands and other elements mounted on the PWB or PCB. The paddle is made of a thermally conductive material and functions as a heat spreader and heat sink device. The paddle can also be used to provide a stable ground for the IC package by using down bonds or an electrically conductive die attach material to provide the electrical ground path from the IC package to the PWB or PCB.
The typical QFN IC package of the type described above is small in size, light in weight, and has a low profile (i.e., small thickness) due to it being generally flat relative to typical IC packages that have leads that rotrude from the bottom or sides of the package. Therefore, the QFN IC package is particularly well suited for use in devices that are small in size, such as small hand-held devices (e.g., cellular telephones, personal digital assistants (PDAs), etc.). In addition, the paddle provides the IC package with very good thermal and electrical performance.
The size of a typical QFN IC package generally depends on the number of lands that are in the package and the size of the IC die. QFN IC packages are available with different numbers of lands, such as, for example, 12 lands, 28 lands, 44 lands, etc. A 12-land QFN IC package may be, for example, 3 millimeters (mm) by 3 mm in size whereas a 28-land package may be, for example 5 mm by 5 mm in size. The die is typically slightly smaller in size than the paddle size for the reasons described above, i.e., to allow for die attach epoxy bleedout and electrical ground bonding. For example, in a 28-land QFN IC package offered by Amkor Technology, Inc., the die is 2.54 mm by 2.54 mm in size while the exposed portion of the paddle is 2.70 mm by 2.70 mm in size. The extra space between the sides of the die and the sides of the paddle provides room for epoxy bleed out from the die attach adhesive and also provides room for wire bonds for grounding the IC to the paddle. The paddle is needed because it provides thermal and electrical pathways needed for good thermal and electrical performance.
FIG. 1 illustrates a bottom plan view of a typical QFN IC package 5 of the type described above having a plurality of lands 6 on each side of the package 5, a die 7, a paddle 8, and a molded plastic body 8. In this example, the die 7 is square in shape in the X and Y dimensions and is mounted on the paddle 8, which is also square in shape in the X and Y dimensions. The die 7 is smaller in the X and Y dimensions than the paddle 8 to allow room for bleedout of the epoxy die attach material used to attach the die 7 to the paddle 8 and to allow room for wire bonding for electrically grounding the die 7 to the paddle 8. The paddle 8 includes an unexposed portion 9A and an exposed portion 9B. The die 7 is attached to the top surface of the unexposed portion 9A of the paddle 8. The bottom surface of the exposed portion 9B of the paddle 8 is soldered to the PWB or PCB (not shown).
FIG. 2 illustrates a side view of a portion of the QFN IC package 5 depicted in FIG. 1. In this example, the die 7 is 7.5 mils (10−3 inches) thick (the Z dimension) and is square shape with a width and length (the X and Y dimensions) of 2.3 mm. The top surface of the unexposed portion 9A of the paddle 8 has a recess 12 formed in it where the die 7 is attached to provide a seat for the die 7 and to contain the die attach material bleedout. The bottom surface of the exposed portion 9B of the paddle 8 is also square in shape and has a width and length (the X and Y dimensions) of 3.8 mm, which equates to an area of about 14.44 mm2. Because the bottom surface of the exposed portion 9B of the paddle is flush with the IC package, after the exposed portion 9B has been soldered to the PCB or PWB, no traces can be routed and no vias can be placed in the portion of the PWB or PCB on which the exposed portion 9B is mounted. This can be a problem because it reduces flexibility with respect to trace routing and via placement, especially in cases where the PWB or PCB is small in size, such as when used in a cellular telephone or PDA, for example. In addition, because the paddle 8 blocks off trace routing and/or via placement, it may be necessary to increase the number of layers of the PCB or PWB or to use a more expensive laminate array package to obtain a desired solution. Accordingly, a need exists for a QFN IC package having a paddle that is configured in such a way that it does not block off PWB or PCB routings or via placements. A need also exists for a method for determining a paddle configuration that allows for trace routing and/or via placement while also providing the aforementioned thermal and electrical performance advantages.